An area efficient memory-less ROM design architecture for direct digital frequency synthesizer
This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA...
| Published in: | International Journal of Electrical and Computer Engineering |
|---|---|
| Main Author: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Advanced Engineering and Science
2021
|
| Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85091148902&doi=10.11591%2fijece.v11i1.pp257-264&partnerID=40&md5=125453d86335e9c826695389fde55ec0 |